1. Field of the Invention
This invention relates to electronic memories and, more particularly, to systems which provide clock signals for reading from said memories.
2. Prior Art
When data is read out of an external electronic memory device, such as for example a dynamic random access memory DRAM, the data is retrieved from the memory core cells and is made available to a user's utilization device only after certain propagation-time delays, which are within the memory device and which are within a user's circuits, have elapsed. Electronic memory devices themselves, such as DRAMS, typically are specified by their manufacturers to have the same access delay time for both a read mode of operation and for a write mode of operation. However, the user's associated circuitry often adds more additional delay to an operation in which the memory is read by the user, in comparison to an operation in which the memory is written by the user. The reason for the unequal delays is that the user in the memory-read mode must not only send signals to the memory (similar to the write mode) but must also receive signals back from the memory, where receipt of the read signals involves additional propagation delays.
Some of the user's propagation delays are the propagation delays for a column-address-strobe CAS signal generated by user to strobe the column address of a previously selected row of information in a memory, where the memory is organized and addressed by row and column address signals. The CAS signal is held in a latching flip-flop, which typically has a small amount of propagation delay. The output signal of the latching flip-flop passes through a CAS-buffer to the CAS input terminal of the electronic memory device. The CAS buffer typically has a greater amount of propagation delay than the latching flip-flop.
Where the CAS signal does not change for every column address, as in a static-column DRAM, the column address signals have propagation delays which must be accounted for as they pass through a user's address circuits.
Another propagation delay is the access time required for memory cell information to appear at the memory output terminals after a particular memory cell is addressed. The user has no control over the memory access-time delay, which is specified by a manufacturer for a particular memory device.
Other user's delays also include the propagation delay through a buffer for receiving the memory output data, which has a relatively large amount of propagation delay, and the propagation delay through a user's read data-latching flip-flop.
In practice, the propagation delays through a user's buffer circuits also depends on variations in the impedance loading, such as capacitance loading, on the various signal lines within a user's application system. Consequently, means (such as fixed delay lines) for providing fixed propagation delays to compensate in some way for propagation delays through a user's buffer circuits, may not simply and adequately provide sufficient delay compensation.
In a write mode of operation, the propagation delays of the various control signals are required to be equal in order to have a cycle time which is equal to the write cycle time of the memory. On the other hand, in a read mode of operation, delays in addition to the memory access time, as described hereinabove, must be accounted for.